募集要項
- 仕事内容
- *SRAM architecture design
*Read and write critical path design and analysis
*Design of key building blocks (sensing, analog, high voltage, DFT)
*Chip-level design verification
*Embedded non-volatile memory compiler and productization
*Co-work with product/reliability engineer on silicon characterization and reliability qualification
- ポジション
- 最大手ファンダリーのMemory Design Engineer and Manager
- 応募条件
-
■求める学歴
大学卒以上
■求める経験
*The candidates should have at least bachelor degree with 10 years of experiences, master degree with 3 years of experience or PhD degree in relevant field.
*Memory experts in the field of SRAM.
*Familiar with bit cell characteristics (Vmin, bit cell performance, write margin), sense amplifier design, high sigma variation analysis, race check, margin signoff.
*Knowledge on high speed and low Vmin design is a plus.
*English is a plus
■マネジメント経験
不要
- 必要スキル
-
■求める英語レベル詳細
ビジネスレベル
- 求める人物像
-
Personal Attributes:
*Self-motivated in learning and problem-solving
* Good communication skill and a good team player
* Strong ownership and commitment
- 雇用形態
-
正社員
- 転勤
-
無
- 勤務地
-
神奈川県横浜市
- 年収
-
700万円~1,200万円
- 休日休暇
-
週休2日(土日)、祝日休、夏休み、年末年始休
- 担当者メッセージ
-
ビジネス好調な世界最大手のファンダリーでご活躍頂けます。
管理コード