募集要項
- 仕事内容
- Report To: Director or Sr. Manager
Role:
*Digital Design Methodology/Flow Development for TSMC advance technologies.
* Responsible for design/technology performance/power/area (PPA) analysis and optimization for TSMC advance technology nodes.
* EDA tools Enablement & Certification
* Customer’s design flow support
Responsibility:
* Design/Technology PPA analysis and optimization
* EDA Tool Enablement & Certification
*Customer’s design flow support
- ポジション
- 最大手ファンダリーのDesign Methodology/Flow Development Mana
- 応募条件
-
■求める学歴
大学卒以上
■求める経験
Requirements:
*Education:
- M.S. degree or above in EE/CS
* Minimum of 3+ years of working experience in digital design, design flow & chip implementation related field.
* Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler) & PPA analysis/boost methodology
*Proven capabilities in design flow development, customer’s design flow support & cross functional communication skill would be preferred.
*Language:
-Proficiency in English is basic requirement. Proficiency in Chinese is a plus.
*Personal Attributes
-Team player with good communication skills, responsibility & flexibility.
-Strong skill to go into technical details to find flow solutions for customers
■マネジメント経験
不要
- 必要スキル
-
■求める英語レベル詳細
ビジネスレベル
■他の言語スキル
中国語尚可
- 雇用形態
-
正社員
- 転勤
-
無
- 勤務地
-
神奈川県横浜市
- 年収
-
700万円~1,200万円
- 休日休暇
-
週休2日(土日)、祝日休、夏休み、年末年始休
- 担当者メッセージ
-
ビジネス好調な世界最大手のファンダリーでご活躍頂けます。
管理コード